Selected Work
A focused archive of RTL, verification, and accelerator design projects.
9T DCIM SRAM Macro
32×32 digital compute-in-memory INT8 matrix-vector macro on a full-custom 9T SRAM bitcell. Full RTL-to-GDS signoff on GF180MCU — DRC/LVS/antenna clean, timing closed across every PVT corner.
INT8 Systolic MAC Array
Output-stationary INT8 systolic array for transformer GEMM. Verified bit-exact across 10,000 random matmuls; closes timing at 100 MHz on Artix-7.
Real-Time FM Software-Defined Radio
Real-time FM SDR on Raspberry Pi 4 — mono, stereo, and RDS from RF. Three-thread pipeline with polyphase resampling, holds real-time at 600 MHz, 101 taps.
RTL Image Decompression Pipeline
JPEG-style FPGA decoder in SystemVerilog on the DE1-SoC at 50 MHz. Four multipliers time-multiplexed across chroma upsampling, YCbCr→RGB, and 2-D IDCT.
ToF 3D Room Scanner
ARM Cortex-M room scanner — stepper motor + VL53L1X time-of-flight sensor, streams distances over UART, renders as a 3D point cloud in Open3D.
OFDM Wireless Transceiver
A software OFDM physical layer in Python — 802.11a-style framing, Zadoff-Chu synchronization, LS channel estimation. Measured BER matches QPSK theory within ~2 dB.