Ratish Gupta
I'm a Computer Engineering student at McMaster (B.Eng., 2023 – 2027). My focus is RTL design, FPGA verification, and ML hardware acceleration. The main thing I'm working on right now is a compute-in-memory transformer accelerator on FPGA. The first milestone, an 8×8 INT8 systolic MAC array, closes timing at 100 MHz with 64 DSP48E1 slices on Artix-7.
My RTL is written in SystemVerilog and verified with cocotb plus Verilator. I run synthesis through Vivado or Quartus depending on the board. Software side, I write C++17 and Python. The most recent of those is a real-time multithreaded FM SDR receiver that decodes mono, stereo, and RDS on a Raspberry Pi. Last summer I interned at the Bank of Montreal as a software developer, mostly on backend microservices and the testing around them.
Honours: Dean's Honour List (2024), Engineering International Scholar Award, Faculty of Engineering Award of Excellence, Dean's Global Distinction. I went to IEEE ISSCC 2026 in San Francisco for the AI accelerator and compute-in-memory sessions.
Disciplines
- HDL & RTL
- SystemVerilog, Verilog, FSM design, datapath & control logic
- Verification
- cocotb, Verilator, ModelSim, QuestaSim, timing analysis, pipelining
- FPGA
- Xilinx Artix-7 (Vivado), Altera DE1-SoC (Quartus Prime), GTKWave
- DSP & Embedded
- Polyphase FIR, PLL/CDR, RDS, ARM Cortex-M, UART / I²C / GPIO, multithreaded systems
- Programming
- C / C++17, Python (NumPy, signal processing), Java, Tcl scripting, Make
- Lab & Debug
- Oscilloscope, logic analyser, LTspice, PSpice, signal-integrity analysis